Professor
Kahlert School of Computing
The University of Utah
E-mail: vijay at cs.utah.edu
Publications
Patents
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Vijay Nagarajan Professor Kahlert School of Computing The University of Utah E-mail: vijay at cs.utah.edu |
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Back to Home Publications Patents |
| Publications |
| 2024 |
| [PACT] |
A. Zhang A. Goens, N. Oswald, T. Grosser, D.J. Sorin, and V. Nagarajan PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model Parallel Architectures and Compilation Techniques, Oct 2024 (to appear) |
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| [ISCA] |
W.Li, A. Goens, N. Oswald, V. Nagarajan, D.J. Sorin Determining the Minimum Number of Virtual Networks for Different Coherence Protocols The International Symposium on Computer Architecture. June'24, to appear. |
| 2023 |
| [Top Picks] |
N. Oswald, V. Nagarajan, D.J. Sorin, V. Gavrielatos, T. Olausson, and R. Carr HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols IEEE MICRO Top Picks, to appear. |
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| [PLDI] |
A. Goens, S. Chakraborty, S. Sarkar, S. Agarwal, N. Oswald and V.Nagarajan Compound Memory Models The 44th ACM SIGPLAN Conference on Programming Language Design and Implementation, June'23. |
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| [DSN] |
A. Patil, V.Nagarajan, N. Nikoleris, and N. Oswald Apta: Fault-tolerant object-granular CXL disaggregated memory for accelerating FaaS The 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, June'23. |
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| [LATTE] |
V. Nagarajan, D.J. Sorin, and N. Oswald Insights from the *Gen Project Workshop on Languages, Tools, and Techniques for Accelerator Design [Video] |
| 2022 |
| [HPCA] |
IEEE MICRO Top Picks N. Oswald, V. Nagarajan, D.J. Sorin, V. Gavrielatos, T. Olausson, and R. Carr HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols The 28th IEEE International Symposium on High-Performance Computer Architecture, April 2022, to appear. [Code] |
| 2021 |
| [ATC] |
M. Bailleu, D. Giantsidi, V. Gavrielatos, V. Nagarajan, and P.Bhatotia Avacado: A Secure In-Memory Distributed Storage System Usenix Annual Technical Conference [Code] |
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| [ISCA] |
A. Patil, V. Nagarajan, R. Balasubramonian, and N. Oswald Dve: Improving DRAM Reliability and Performance On-Demand with Coherent Replication 48th IEEE/ACM International Symposium on Computer Architecture [Code] |
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| [EuroSys] |
V. Gavrielatos, A. Katsarakis, and V. Nagarajan Odyssey: The Impact of Modern Hardware on Strongly-Consistent Replication Protocols The European Conference on Computer Systems [Code] [Detailed Paxos + All Aboard + Carstamps Specification] |
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| [PaPoC] |
V. Gavrielatos, V. Nagarajan, and P. Fatourou Towards the Synthesis of Coherence/Replication Protocols from Consistency Models via Real-Time Orderings. 8th Workshop on Principles and Practice of Consistency for Distributed Data |
| 2020 |
| [ISCA] |
N. Oswald, V. Nagarajan and D.J. Sorin HieraGen: Automatically Generating Hierarchical Cache Coherence Protocols from Atomic Specifications The 47th International Symposium on Computer Architecture, June 2020, to appear. |
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| [PPoPP] |
One of the 5 best paper candidates V. Gavrielatos, A. Katsarakis, V. Nagarajan, B. Grot and A. Joshi Kite: Efficient and Available Release Consistency for the Datacenter The 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. [Code] |
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| [ASPLOS] |
IEEE MICRO Top Picks Honourable Mention A. Katsarakis, V. Gavrielatos, M.R.S. Katebzadeh, A. Joshi, A. Dragojevich, B. Grot and V. Nagarajan Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol The 25th International Conference on Architectural Support for Programming Languages and Operating Systems [Code] |
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| [ASPLOS] |
M. Dananjaya, V. Gavrielatos, A. Joshi, and V. Nagarajan Lazy Release Persistency The 25th International Conference on Architectural Support for Programming Languages and Operating Systems [Code] |
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| [Synthesis Lectures] |
V. Nagarajan, D. J. Sorin, M. D. Hill, and D. A. Wood A Primer on Memory Consistency and Cache Coherence, Second Edition Synthesis Lectures on Computer Architecture, Morgan and Claypool. |
| 2019 |
| [HPCA] |
S. Dublish, V. Nagarajan and N. Topham Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning 25th IEEE International Symposium on High-Performance Computer Architecture, Feb 2019, to appear. |
| 2018 |
| [ISCA] |
IEEE MICRO Top Picks Honourable Mention N. Oswald, V. Nagarajan and D.J. Sorin ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications The 45th International Symposium on Computer Architecture, June 2018. [Code] |
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| [ISCA] |
A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas DHTM: Durable Hardware Transactional Memory The 45th International Symposium on Computer Architecture, June 2018. |
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| [EuroSys] |
V. Gavrielatos, A. Katsarakis, A. Joshi, N. Oswald, B. Grot, and V. Nagarajan Scale-Out ccNUMA: Exploiting Skew with Strongly Consistent Caching The 13th European Conference on Computer Systems, April 2018. [Code] |
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| [ASPLOS] |
R. Kumar, B. Grot, and V. Nagarajan Blasting Through The Front-End Bottleneck with Shotgun The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems, March 2018. |
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| [DATE] |
M. Elver, C. J. Banks, P. Jackson, and V. Nagarajan VerC3: A Library for Explicit State Synthesis for Concurrent Systems Design, Automation and Test in Europe, March 2018. [Code] |
| 2017 |
| [FMCAD] |
C. J. Banks, M. Elver, R. Hoffmann, S. Sarkar, P. Jackson, and V. Nagarajan Verification of a lazy cache coherence protocol against a weak memory model (preprint) The 17th Conference on Formal Methods in Computer-Aided Design, Oct 2017. [Code] |
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| [ISPASS] |
S. Dublish, V. Nagarajan and N. Topham Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs IEEE International Symposium on Performance Analysis of Systems and Software San Francisco, April 2017. |
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| [HPCA] |
A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas ATOM: Atomic Durability in Non-volatile Memory through Hardware Support for Logging The 23rd IEEE Symposium on High Performance Computer Architecture Austin, Texas, USA Feb 2017. |
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| [HPCA] |
R. Kumar, C. Huang, B. Grot, and V. Nagarajan Boomerang: a Metadata-Free Architecture for Control Flow Delivery The 23rd IEEE Symposium on High Performance Computer Architecture Austin, Texas, USA Feb 2017. |
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| [TACO] |
S. Dublish, V. Nagarajan and N. Topham Cooperative Caching for GPUs ACM Transactions on Architecture and Code Optimization Also invited presentation at HiPEAC 2017, Stockholm, Sweden, Jan 2017. |
| 2016 |
| [MICRO] |
C. Huang, R. Kumar, M. Elver, B. Grot, and V. Nagarajan C3D: Mitigating NUMA Effects via Coherent DRAM Caches The 49th ACM/IEEE International Symposium on Microarchitecture, Taipei, Taiwan, October 2016. [C3D Specification and Murphi Model] |
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| [SC] |
C. Huang, V. Nagarajan and A. Joshi DCA: a DRAM-cache-aware DRAM controller The IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis, Salt Lake City, USA November 2016. |
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| [IROS] |
J. Cano, A. Bordallo, V. Nagarajan, S. Ramamoorthy, and S. Vijayakumar Automatic Configuration of ROS Applications for near-optimal Performance IEEE/RSJ International Conference on Intelligent Robots and Systems Korea, October 2016 (to appear). |
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| [RSS] |
J. Cano, D. White, A. Bordallo, C. McCreesh, P. Prosser, J. Singer and V. Nagarajan Task Variant Allocation in Distributed Robotics Robotics: Science and Systems Ann Arbor, USA, June 2016. [Code] |
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| [HPCA] |
M. Elver and V. Nagarajan McVerSi: A Test Generation Framework for Fast Memory Consistency Verification in Simulation The 22nd Symposium on High Performance Computer Architecture Barcelona, Spain March 2016. [Simulator-independent library] |
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| [TACO] |
A. J. McPherson, V. Nagarajan, S. Sarkar and M. Cintra Fence placement for legacy data-race-free programs via synchronization read detection ACM Transactions on Architecture and Code Optimization, January 2016. Also appeared as PPoPP Poster, Feb 2015. |
| 2015 |
| [MICRO] |
A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas Efficient Persist Barriers for Multicores The 48th Annual IEEE/ACM International Symposium on Microarchitecture Waikiki, Hawaii, USA Dec 2015. |
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| [PACT] |
M. Elver and V. Nagarajan RC3: Consistency directed Cache Coherence for x86-64 with RC extensions The 24th International Conference on Parallel Architectures and Compilation Techniques San Francisco, USA Oct 2015. |
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| [SAFECOMP] |
G. Stefanakis, V. Nagarajan, and M. Cintra Understanding the Effects of Data Corruption on Application Behavior Based on Data Charecterestics International Conference on Computer Safety, Reliability and Security Delft, Netherlands Sep 2015. |
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| [ICAR] |
J. Cano, E. Molinos, V. Nagarajan, and S. Vijayakumar Dynamic process migration in heterogeneous ROS-based environments The 17th International Conference on Advanced Robotics Istanbul, Turkey July 2015. |
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| [NVMW] |
M. Cintra, A. Chatzistergiou, A. Joshi, V. Nagarajan, and S. Viglas DAPPER: a database-inspired approach to persistent memory Non-Volatile Memories Workshop San Diego, USA March 2015. |
| 2014 |
| [SC] |
C. Lin, V. Nagarajan and R. Gupta Fence Scoping The IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis, New Orleans, USA November 2014. |
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| [ICCD] |
C. Huang and V. Nagarajan Increasing Cache Capacity via Critical-words-Only Cache The 32nd IEEE International Conference on Computer Design, Seoul, Korea October 2014. |
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| [LCPC] |
A. J. McPherson, V. Nagarajan, and M. Cintra Static Approximation of MPI Communication Graphs for Optimized Process Placement The 27th International Workshop on Languages and Compilers for Parallel Computing, Hilsboro, September 2014. |
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| [PACT] |
C. Huang and V. Nagarajan ATCache: Reducing DRAM cache Latency via a Small SRAM Tag Cache The 23rd International Conference on Parallel Architectures and Compilation Techniques, Edmonton, Canada, August 2014. |
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| [HPCA] |
M. Elver and V. Nagarajan TSO-CC: Consistency directed cache coherence for TSO The International Symposium on High-Performance Computer Architecture, Orlando, USA Feb 2014. [TSO-CC Specification] |
| 2013 |
| [PLDI] |
B. Rajaram, V. Nagarajan, S. Sarkar, and M. Elver Fast RMWs for TSO: Semantics and Implementation ACM SIGPLAN Conference on Programming Language Design and Implemenation, Seattle, Washington, June 2013. |
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| [ICS] |
C. Lin, V. Nagarajan, and R. Gupta Address-aware Fences 27th International Conference on Supercomputing, Eugene, Oregon, June 2013 |
| 2012 |
| [ACM CF] |
B. Rajaram, V. Nagarajan, A. J. McPherson, and M. Cintra SuperCoP: A General, Correct, and Performance-efficient Supervised Memory System, ACM International Conference on Computing Frontiers, May 2012. |
| [ASPLOS] |
C. Lin, V. Nagarajan, R. Gupta and B. Rajaram Efficient Sequential Consistency via Conflict Ordering, ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems, March 2012. |
| [ASPLOS poster] |
Received 2nd prize: Best Poster B. Rajaram and V. Nagarajan Fast RMWs for TSO, ACM 17th International Conference on Architectural Support for Programming Languages and Operating Systems, Poster session. |
| 2011 |
| [SP&E] |
V. Nagarajan, D.Jeffrey, and R.Gupta A System for Debugging via Online Tracing and Dynamic Slicing, Software - Practice & Experience, July 2011. |
| [IJPP] |
C.Lin, V. Nagarajan, and R.Gupta Efficient Sequential Consistency Using Conditional Fences, International Journal of Parallel Programming, June 2011. |
| 2010 |
| [PACT] |
Received a Best Paper Award C.Lin, V. Nagarajan, and R.Gupta Efficient Sequential Consistency Using Conditional Fences, The 19th International Conference on Parallel Architectures and Compilation Techniques, Vienna, Austria, September 2010. |
| [TOPLAS] |
D.Jeffrey, V. Nagarajan, and R.Gupta Execution Supression: An Automated Iterative Technique for locating Memory Errors, ACM Transactions on Programming Languages and Systems, Vol. 32, No. 5, 36 pages, May 2010. |
| 2009 |
| [LCPC] |
V. Nagarajan and R.Gupta, Speculative Optimizations for Parallel Programs on Multicores, 22nd International Workshop on Languages and Compilers for Parallel Computing, Newark, Delaware, October 2009. |
| [IJPP] |
C. Tian, M.Feng, V. Nagarajan and R. Gupta, Speculative Parallelization of Sequential Loops On Multicores, International Journal of Parallel Programming, October 2009. |
| [SP&E] |
C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Automated Dynamic Detection of Busy-wait Synchronizations, Software - Practice and Experience, August 2009. |
| [ISCA] |
V. Nagarajan and R.Gupta, ECMon: Exposing Cache Events for Monitoring, ACM/IEEE 36th International Symposium on Computer Architecture, Austin, Texas, June 2009. |
| [ISMM] |
V. Nagarajan, D. Jeffrey and R. Gupta, Self Recovery in Server Programs, International Symposium on Memory Management, Dublin, Ireland, June 2009. |
| [SIGOPS] |
V. Nagarajan and R.Gupta, Runtime Monitoring on Multicores via OASES, ACM SIGOPS Operating Systems Review, special issue on the interaction among the OS, Compilers, and Multicore Processors, 10 pages, April 2009 (Invited Paper). |
| [VEE] |
V. Nagarajan and R.Gupta, Architectural Support for Shadow Memory in Multiprocessors, ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 10 pages, Washington DC, March 2009. |
| [Trans. HiPEAC] |
V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors Transactions on High Performance Embedded Architectures and Compilers, Vol. 2, No. 1, pages 23-44, Springer Verlag, 2009 (Invited Paper -- special issue of selected papers from HiPEAC Conference). |
| 2008 |
| [MICRO] |
C. Tian, M. Feng, V. Nagarajan, and R. Gupta, Copy or Discard Execution Model For Speculative Parallelization On Multicores, IEEE/ACM 41st International Symposium on Microarchitecture, pages 330-341, Lake Como, Italy, Nov. 2008. |
| [ISSTA] |
C. Tian, V. Nagarajan, R. Gupta, and S. Tallam, Dynamic Recognition of Synchronization Operations for Improved Data Race Detection, SIGSOFT International Symposium on Software Testing and Analysis, pages 143-154, Seattle, July 2008. |
| [PADTAD] |
V. Nagarajan and R.Gupta, Support for Symmetric Shadow Memory in Multiprocessors, Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, (colocated with ISSTA), 9 pages, Seattle, July 2008. |
| [STMCS] |
C. Tian, V. Nagarajan, and R. Gupta, Synchronization Aware Conflict Resolution for Runtime Monitoring Using Transactional Memory, Workshop on Software Tools for Multicore Systems, (colocated with CGO), 6 pages, Boston, April 2008. |
| [NSFNGS] |
R. Gupta, N. Gupta, X. Zhang, D. Jeffrey, V. Nagarajan, S. Tallam and C. Tian Scalable Dynamic Information Flow Tracking and its Applications, NSF Next Generation Software Workshop, colocated with IPDPS, pages 1-5, Florida, April 2008. |
| [INTERACT] |
V. Nagarajan, H-S.Kim, Y.Wu and R. Gupta, Dynamic Information Flow Tracking on Multicores, Workshop on Interaction between Compilers and Computer Architectures, (colocated with HPCA), 10 pages, Salt Lake City, Feb. 2008. |
| 2007 |
| [ICSM] |
V. Nagarajan, D. Jeffrey, R. Gupta and N. Gupta ONTRAC: A System for Efficient ONline TRACing for Debugging, International Conference on Software Maintenance, pages 445-454, Paris, September 2007. |
| [ICSM] |
V. Nagarajan, R. Gupta, X. Zhang, M. Madou, and B. De Sutter Matching Control Flow of Program Versions, International Conference on Software Maintenance, pages 84-93, Paris, September 2007. |
| [HiPEAC] |
V.Nagarajan, R. Gupta, and A.Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors International Conference on High Performance Embedded Architectures and Compilers, Springer Verlag, LNCS 4367, pages 7-22, Ghent, Belgium, January 2007. |
| Patents |
Software Flow Tracking using Multiple threads.
Inventors: V. Nagarajan, H-S. Kim (Intel), Y. Wu (Intel), and R. Gupta, US Patent 8,321,840 .