Rajeev Balasubramonian

My research focuses on many aspects of computer architecture. I am especially interested in studying how future technology trends influence the design of microprocessors and memory systems. In recent years, we have focused on designing memory systems that can cater to the bandwidth, latency, power, cost, security, and reliability demands of data-intensive workloads. We are also exploring accelerators for a range of demanding kernels, including deep neural networks, genomic analysis, and security primitives. Current projects include:

Past projects include:

As a graduate student, I delved into problems involving memory hierarchy bottlenecks ( MICRO'00 ), pre-execution threads ( ISCA'01 ), register file complexity ( MICRO'01 ), and scalability of clustered microprocessors ( ISCA'03 ). Ph.D. Thesis.

Full publication list (in chronological order)




Software Release

HEPack Simulator




Book and Book Chapters

Research projects and corresponding publications

Most publications are copyrighted by IEEE or ACM. Please respect these copyrights. Typically, personal or classroom use is granted; papers cannot be duplicated for commercial purposes. In recent years, the research group has been funded by NSF grant CCF-0430063, NSF CAREER award CCF-0545959, NSF grant CCF-0811249, NSF grant CCF-0916436, NSF grant CNS-1302663, NSF grant CNS-1423583, NSF grant CNS-1718834, NSF grant CCF-2119677, SRC Contract 2008-TJ-1847, Intel, Google, HP Labs, IBM, Samsung, and the University of Utah. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or any other sponsor. Some of our simulation results are derived with Simics that is supported by Virtutech .

Calvin's take on research