Digital VLSI Chip Design
with Cadence and Synopsys
CAD Tools


By Erik Brunvand


Please note that all this information is provided "as is" and without any warranty of any kind. Please use the information at your own risk. This warning is especially true of the cell libraries!

This is a very basic example CMOS cell library that can be used with the examples in the book. It has only seven cells: DFF, FILL, INVX1, NAND2X1, NOR2X1, TIEHI, and TIELO. But, it's fully functional and works with the entire flow described in the book. You can use it with Synopsys Design Compiler or Cadence RTL Compiler to synthesize a circuit (Chapter 9). You can simulate the resulting circuit using Verilog-XL, NC_Verilog, or VCS (See Chapter 4) You can use it with the SOC Encounter place and route tool (Chapter 11). You can make a whole chip with it (at your own risk, of course)! (Chapter 13). It includes cmos_sch, behavioral, symbol, extracted, analog_extracted, and abstract views. It also includes UofU_Example.lib, .lef, .db, and .v files for use with the various parts of the design flow described in the book.

The UofU_Example cell library now comes in two flavors: CDB for use with Cadence IC v5, and OA for use with Cadence IC v6

To use the library, simply untar the UofU_Example directory from the gzipped tar file. Then point to the location where you put the UofU_Example library directory in your cds.lib file. You can put this in the NCSU CDK cds.lib file in $CDK_DIR/cdssetup/cds.lib, or in the $LOCAL_CADSETUP/cadence/cds.lib file, or in the cds.lib file that is in the directory from which you start the Cadence tools. The format in the cds.lib file is:

DEFINE UofU_Example <path-to-the-directory>/UofU_Example

Note that this cell library is designed for use in the ON (formerly AMI) C5N 0.5 micron CMOS process using the MOSIS SCN3M_SUBM design rules. It uses the UofU_TechLib_ami06 technlogy, and the devices in the cmos_sch views use the transistors from the UofU_Analog_Parts library. These are the same as the transistors in the NCSU_Analog_Parts library, but include 0.1 units of delay on each device when simulated using a Verilog simulator (see Chapter 4). If you have NOT installed UofU_Analog_Parts, you can use the Edit->RenameReferenceLibrary command in the Library Manager to change all references to UofU_Analog_Parts to be NCSU_Analog_Parts instead for the entire library. The NCSU_Analog_Parts transistors result in zero-delay transistors for simulation.


Last modified May 18, 2011.