Digital VLSI Chip Design
with Cadence and Synopsys
CAD Tools


By Erik Brunvand



Please note that all this information is provided "as is" and without any warranty of any kind. Please use the information at your own risk. This warning is especially true of the cell libraries!

This is a small library that contains transistor cells (nmos and pmos) copied from the NCSU_Analog_Parts library. The NCSU versions have zero delay when simulated with a Verilog simulator. The UofU versions have been modified to have 0.1 units of delay when simulated using Verilog. I find that this makes a much more realistic simulation and can help spot certain types of delay issues in the circuit. You do have to beware, however, of forgetting that this is an abstract "unit delay" type of simulation and thinking of this in ns. It's not!

The UofU_Analog_Parts library now comes in two flavors: CDB for use with Cadence IC v5, and OA for use with Cadence IC v6

To use, uncompress and untar the UofU_Analog_Parts library from the gzipped tar file. Put that directory somewhere where people can access it, and then point to it in your cds.lib file. You can put this in the NCSU CDK cds.lib file in $CDK_DIR/cdssetup/cds.lib, or in the $LOCAL_CADSETUP/cadence/cds.lib file, or in the cds.lib file that is in the directory from which you start the Cadence tools. The format in the cds.lib file is:

DEFINE UofU_Analog_Parts <path-to-the-directory>/UofU_Analog_Parts

The cells defined in UofU_Analog_Parts are (see section 4.4.4 in the book for more details):

Last modified May 18, 2011.