CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories


CACTI 7 is an extended version of CACTI that includes power, area and timing models for I/O. CACTI 7 allows for a quick search of optimal IO configuration parameters that help optimize power and performance of the IO along with the DRAM and cache subsystem. CACTI has analytical models for all the basic building blocks of a memory: decoder, sense-amplifier, crossbar, on-chip wires, DRAM/SRAM cell, and latch. We extend it to include the OFF-chip models. This requires modifying CACTI's global on-chip interconnect to include buffers at the PHY and drivers at the bank edge to connect to the IO circuit. Since all calculations are based on the ITRS technology parameters, the energy and delay values calculated by CACTI are guaranteed to be mutually consistent. When a user inputs memory parameters and energy/delay constraints into CACTI, the tool performs an exhaustive design space exploration involving different array sizes, degrees of multiplexing, and interconnect choices to identify an optimal configuration. CACTI 7 is capable of performing an additional search for OFF-chip parameters, including optimal number of ranks, memory data width (x4, x8, x16, or x32 DRAMs), OFF-chip bus frequency, and bus width. This allows for optimal tradeoffs between OFF-chip power, area, and timing. For further details on the off-chip I/O models used in CACTI 7, please refer to the CACTI-IO tech report.

Further, CACTI 7 makes it easy to explore the design space for various types of DIMM configurations, including UDIMM, RDIMM, and LRDIMM. It also includes an API that makes it easy to carry out design space exploration for modern and emerging memory topologies, while correctly modeling I/O power as a function of various parameters. CACTI 7 supports DDR4 and SERDES options for the I/O. It also allows users to define/evaluate non-standard topologies and interconnects for a custom memory system. A description of this design space exploration and potential use cases can be found in this ACM TACO article.


The CACTI 7 github repository.


  1. CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories , Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas, ACM TACO (to appear), 2017.
  2. CACTI-IO: CACTI with Off-chip Power-Area-Timing Models , N. Jouppi, A. B. Kahng, N. Muralimanohar, V. Srinivas, Proc. IEEE/ACM International Conference on Computer-Aided Design, 2012.


CACTI 7 includes power, area and timing models for I/O in the memory system, explores the design space, and gives the user the ability to define new types of memory interconnects/topologies. The tool is validated against SPICE models and enables design space exploration of off-chip I/O for memory interfaces.

CACTI 6.5 is a significantly enhanced version that primarily focuses on interconnect design. In addition to a new streamlined code base with numerous bug fixes, 6.5 includes the following extensions over 5.3. 1) The ability to model different types of wires, such as RC based wires with different power, delay, and area characteristics and differential low-swing buses. 2) Ability to model Non-Uniform Cache Access (NUCA) for chip multiprocessors that takes into account the effect of network contention during the design space exploration. 3) Power model for router components. 4) Improved design space exploration that takes into account different wire types and router types (for NUCA). 5) Improved API to specify constraints involving power, delay, area, and bandwidth. 6) Improved analytical models for dominant cache components such as wordlines and bitlines.

The technical report of CACTI 6.0 (available here) details the new features added to the tool along with a validation analysis of the newly added components. CACTI 6.5 can be downloaded from here.

CACTI 5 includes a number of major improvements over CACTI 4. First, as fabrication technologies enter the deep-submicron era, device and process parameter scaling has become non-linear. To better model this, the base technology modeling in CACTI 5 has been changed from simple linear scaling of the original CACTI 0.8 micron technology to models based on the ITRS roadmap. Second, embedded DRAM technology has become available from some vendors, and there is interest in 3D stacking of commodity DRAM with modern chip multiprocessors. As another major enhancement, CACTI 5 adds modeling support of DRAM memories. Third, to support the significant technology modeling changes above and to enable fair comparisons of SRAM and DRAM technology, the CACTI code base has been extensively rewritten to become more modular. At the same time, various circuit assumptions have been updated to be more relevant to modern design practice. Finally, numerous bug fixes and small feature additions have been made. A tech report on CACTI 5 is available here. CACTI 5.3 is a version of CACTI 5 written in C++, multithreaded with Pthreads, and with various bug fixes. CACTI 5.3 source code can be downloaded here.

CACTI 4.0 adds a leakage power model and updates the basic circuit structures and device parameters to better reflect recent advances in semiconductor scaling. CACTI 4.0 also adds support for greater parameterization, such as user defined tag and data widths, a serial tag and data access option for low power, and modeling of memory structures without tags. A tech report on CACTI 4.0 is available here. CACTI 4.1 fixes a small number of bugs in CACTI 4.0. For users that need to modify CACTI or integrate it into other tools to support their research, CACTI 4.1 source code can be downloaded here.

CACTI 3.0 includes modeling support for the area of caches, caches with independently addressed banks, reduced sense-amp power dissipation and other improvements to CACTI 2.0. A paper describing the CACTI 3.0 improvements to CACTI 2.0 is available in both postscript and pdf formats. CACTI 3.0 tarball can be downloaded here. CACTI 3.2 is a version of CACTI 3.0 with a number of small bug fixes. CACTI 3.2 can be downloaded here.

CACTI 2.0 added modeling support for fully-associative caches, a power model, technology scaling, multiported caches, and improved tag comparison circuits, as well as other improvements to CACTI 1.0. A paper describing the CACTI 2.0 enhancements to CACTI 1.0 is available in both postscript and pdf formats. CACTI 2.0 continues to be made available for use in regression studies and verification of previous work using CACTI 2.0. CACTI 2.0 tarball can be downloaded here.

A detailed description of the original CACTI 1.0 model is given in the CACTI technical report.

CACTI 1.0 was originally developed by Steve Wilton and Norm Jouppi. CACTI 2.0 was developed by Glenn Reinman and Norm Jouppi. CACTI 3.0 was developed by Premkishore Shivakumar and Norm Jouppi. CACTI 4 was developed by David Tarjan, Shyamkumar Thoziyoor, and Norm Jouppi. CACTI 5 was developed by Shyamkumar Thoziyoor, Naveen Muralimanohar, Jung Ho Ahn, and Norm Jouppi. CACTI 6 was developed by Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi. CACTI 7 was developed by Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, and Vaishnav Srinivas.