Lab Objective

To give us a taste of VLSI, this lab taught us a basic set of skills to do full-custom VLSI by drawing the schematic and performing electrical simulations of a “CMOS inverter” using TSMC’s 180nm design kit.

To make this inverter, we used a software package called Virtuoso, which is made by Cadance. I won’t dive too deep into the specific of this software (There’s already lot to talk about), but if you’re still curious, here’s the link to the lab, which goes into the command line details.

What is CMOS technology?

If you’re a PC hobbyist like me, you might have heard of a CMOS battery before. Without that battery, the clock on your desktop might slip a couple hours when you turn it off, and you might miss your next meeting. Well, it turns out that CMOS can do a lot more than keep track of time.

CMOS (Complementary metal-oxide-semiconductor) technology is a methodology for creating the basic building blocks of a chip. A CMOS setup consists of two or more MOSFETs (metal oxide semiconductor field effect transistors) which work together to perform a particular piece of logic. You can use CMOS to create AND gates, OR gates, XOR, NOR, NAND, and Inverter gates, as well as a bunch of other things.

CMOS works by creating a pull up network and a complementary pull down network. The “pull up network” connects a high signal to the output when the logical operation you’re trying to build should output a 1 (a high signal). The “pull down network” connects the output of the gate to ground when the logic gate should return a 0 (a low value). The transistors which form these networks act like electrical switches to connect the high or low signals to the output depending on the input.

The two switches we used are called “PMOS” and “NMOS” transistors. The PMOS switch is on by default, but will turn off when “switched”. The NMOS on the other hand is off by default, and can be turned on when “switched”. (I always get these backwards somehow…) In actuality, the switches are flipped by supplying a voltage to the transistor “gate”. By supplying a positive voltage to a transistor gate, you either fill or empty a mesh with a bunch of holes in it, which either creates or destroys a bridge connecting the top and bottom of the switch. The mesh is actually “doped silicon”, and that bridge is called the “channel” of a transistor. I’m oversimplifying things a bit, but that’s the mental model I use.

Transistor Physics

Since we’re going to use NMOS and PMOS transistors together, we’d like to figure out how quickly these transistors turn on and off, and how width and voltage effects this delay.

Here are some curves plotting voltage applied to the gate of a NAND (along x) against the amperage allowed to pass through the channel (along y) for several NAND gates (NMOS on the right, PMOS on the left) of different widths. (Width from 240nm to 1500nm). The PMOS plot was flipped on both X and Y for easier response comparison.

These plots show us that transistors gradually turn on as more and more voltage is applied to a gate, and that larger width transistors tend to turn on slower (larger channel to fill) but are capable of outputting a much larger current. They don’t turn on linearly either.

At the very beginning, when there isn’t much voltage on our transistor gate, electrons slowly begin to fill the doped silicon (the channel) connecting the source of the transistor to the drain of the transistor. As that channel fills up, more and more current can flow. This gives you some intuition on why a transistor gate is called a “gate”. It’s like we’re lifting a wall and slowly letting water trickle from a source through a channel and out a drain.

One tricky thing about electrons though is that they’re polarised, and attract each other. As we apply a voltage to the source of our “switch”, we attract electrons in the channel more to the source side rather than the drain side. As a result, our channel fills unevenly. Eventually the channel fills up completely, but overall this effects how quickly the switch will turn on. Here’s a table explaining the different characteristics our transistors will go through:

There’s also a variation on how quickly a NMOS turns on compared to a PMOS, so we’ll need to account for this by increasing the width of one to compensate for the other.

The CMOS inverter

Here’s the schematic for a CMOS inverter, which flips the input at the output. A 1 on the input results in a 0 at the output, and vice versa.

Edges represent electrical wires. A is our input wire, and Z is our output wire.

Our input signal is connected to the gates of both the pull up network (a single PMOS) and pull down network (a single NMOS). When the input is high, the PMOS closes the connection from VDD (high signal) to our output. At the same time, a positive input turns on the NMOS, connecting the output to ground.

Voltage Transfer Characteristics

Here’s a plot showing how our inverter works as we apply more and more voltage to the input gate. The different colors represents different widths of the PMOS to try to balance out the NMOS. If we wanted our input to invert the output at the exact midway point (9 volts), we’d need the PMOS width to be roughly 940nm (pink line). That’s wide, which is a problem, since width increases something called parasitic capacitance. In practice we can settle for a PMOS which is double the size of an NMOS (440nm, the green line in the middle), since it’s a good compromise between keeping responses balanced and keeping transistors small.

Timing

Finally, we want to measure how quickly we can turn our inverter on and off.

Here are some timing results testing our inverter with the doubly sized PMOS to roughly balance out the NMOS. The input to the inverter is plotted in blue and the output is plotted in red.

To benchmark this performance, we use three metrics. The first is falling delay, which measures how long it takes to go from 90% on to 10% on. Here we’re seeing a falling delay of roughly 115ps.

The second metric we use is rising delay, which measures how long it takes to go from 10% on to 90% on. Rising delay is slightly longer than falling delay at 192ps. This difference between rising and falling delay is due to the slight skew between the NMOS and PMOS transistors. These delays would be equal if the transistors were perfectly balanced.

The final metric we use is called propagation delay, which measures how long it takes for the input signal to propagate a result to the output signal. This can be measured in two ways. We can measure how long it takes from the input going low to the output going high. We can also measure how long it takes from the input going high to the output going low. Propagation delay from low to high is roughly 70.79ps and from high to low takes roughly 101.12 ps.

We can use all this information to determine how quickly we can operate our inverter. From these results, we could switch the inverter on and off with a period of slightly more than 100ns.