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# Script for Cadence RTL Compiler synthesis      
# Erik Brunvand, 2008
# Use with syn-rtl -f <rtl-script>
######################################################

# Set the search paths to the libraries and the HDL files
# Remember that "." means your current directory
set_attribute hdl_search_path {./} ;# Search path for Verilog files
set_attribute lib_search_path {./} ;# Search path for library files
set_attribute library [list UofU_Digital_v1_2.lib] ;# Target Library
set_attribute information_level 6 ;# See a lot of warnings. 

set myFiles [list moore.v]   ;# All your HDL files
set basename moore           ;# name of top level module
set myClk clk                ;# clock name
set myPeriod_ps 10000        ;# Clock period in ps
set myInDelay_ps 250         ;# delay from clock to inputs valid
set myOutDelay_ps 250        ;# delay from clock to output valid
set runname RTL              ;# name appended to output files

#*********************************************************
#*   below here shouldn't need to be changed...          *
#*********************************************************

# Analyze and Elaborate the HDL files
read_hdl ${myFiles}
elaborate ${basename}

# Apply Constraints and generate clocks
set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]]	
external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*]
external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*]

# Sets transition to default values for Synopsys SDC format, 
# fall/rise 400ps
dc::set_clock_transition .4 $myClk

# check that the design is OK so far
check_design -unresolved
report timing -lint

# Synthesize the design to the target library
synthesize -to_mapped

# Write out the reports
report timing > ${basename}_${runname}_timing.rep
report gates  > ${basename}_${runname}_cell.rep
report power  > ${basename}_${runname}_power.rep

# Write out the structural Verilog and sdc files
write_hdl -mapped >  ${basename}_${runname}.v
write_sdc >  ${basename}_${runname}.sdc
quit