/* D-latch with active high gate (clock) signal, active low clear */ latch(IQ, IQN) { enable : "GATE" ; data_in : "D" ; clear : "CLR'" ;} /* set-reset (SR) latch with active-low set and reset */ latch(IQ, IQN) { clear : "S'" ; preset : "R'" ; clear_preset_var1 : L ; clear_preset_var2 : L ;}