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# Synopsys Design Compiler synthesis script
# Erik Brunvand, Univeristy of Utah
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#
# Target library list should include all target .db files       
set target_library [list UofU_Digital_v1_2.db]

# Synthetic library is DesignWare from Synopsys which has
# details of arithmetic functions (among other things)
set synthetic_library [list dw_foundation.sldb]
set synlib_wait_for_design_license [list "DesignWare-Foundation"]

# Link library is a list of libraries to link the design against
set link_library [concat  [concat  "*" $target_library]
  $synthetic_library]

# Generic symbols from Synopsys
set symbol_library [list generic.sdb]

# below are parameters that you will want to set for each design 

# list of all HDL files in the design                           
set myFiles [list mips.v] ;# All the mips Verilog in one file
set fileFormat verilog    ;# verilog or VHDL
set basename mips         ;# Top-level module name
set myClk clk             ;# The name of your clock 
set virtual 0             ;# 1 if virtual clock, 0 if real clock

# compiler switches...                                  
set useUltra 1            ;# 1 for compile_ultra, 0 for compile

# Timing and loading information                                
set myPeriod_ns 5         ;# desired clock period (sets speed goal)
set myInDelay_ns 0.25     ;# delay from clock to inputs valid
set myOutDelay_ns 0.25    ;# delay from clock to output valid
set myInputBuf INVX4      ;# name of cell driving the inputs
set myLoadLibrary UofU_Digital_v1_2 ;# name of lib the cell is from
set myLoadPin A           ;# name of pin that outputs drive

# Control the writing of result files                           
set runname struct        ;# Name appended to output files

# the following control which output files you want. They       
# should be set to 1 if you want the file, 0 if not             
set write_v 1           ;# compiled structural Verilog file
set write_ddc 1         ;# compiled file in ddc format (XG-mode)
set write_sdf 0         ;# sdf file for back-annotated timing sim
set write_sdc 1         ;# sdc constraint file for place and route
set write_rep 1         ;# report file from compilation
set write_pow 0         ;# report file for power estimate