##########################################################
#  SOC Encounter Top-level Command script                #
#  (Erik Brunvand, 2008)                                 #
##########################################################
# set the BASENAME for the config files. This will also 
# be used for the .lib, .lef, .v, and .spef files
# that are generated by this script
set BASENAME "counter"

# set the name of the filler cells 
set fillerCells [list FILL FILL2 FILL4 FILL8]

set usepct 0.70 ;# percent utilization in placing cells
set rowgap 18   ;# gap between pairs of std cell rows
set aspect 0.50 ;# aspect ratio of overall cell (1.0 is square)
# less than 1.0 is landscape, greater than 1.0 is portrait

#############################################################
# You may not have to change things below this line - but check!
#############################################################
set clockBufName inv ;# Footprint of inverter in .lib file

# Note that all these numbers should  be divisible by 3 so 
# that they fit on the lambda grid
set pwidth 9.9    ;# power rail width
set pspace 1.8    ;# power rail space
set swidth 4.8    ;# power stripe width
set sspace 99     ;# power stripe spacing
set soffset 120   ;# power stripe offset to first stripe
set coregap 30.0  ;# gap between the core and the power rails 

# Import design and floorplan from a config file
# If the config file is not named $BASENAME.conf, edit this line. 
loadConfig $BASENAME.conf 0
commitConfig

# source the other files that operate on the circuit
source fplan.tcl  ;# create the floorplan (might be done by hand...)
source pplan.tcl  ;# create the power rings and stripes
source place.tcl  ;# Place the cells and optimize (pre-CTS)
source cts.tcl    ;# Create the clock tree, and optimize (post-CTS)
source route.tcl  ;# Route the design using nanoRoute
source verify.tcl ;# Verify the design and produce output files
exit