################################################
#  Encounter Input configuration file          #
#  Erik Brunvand, University of Utah           #
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global rda_Input
#
#########################################################
# Here are the parts you need to update for your design
#########################################################
#
# Your input is structural verilog. Set the top module name 
# and also give the .sdc file you used in synthesis for the 
# clock timing constraints. Also an io file if used. 
set rda_Input(ui_netlist)        {counter_struct.v}
set rda_Input(ui_topcell)        {counter}
set rda_Input(ui_timingcon_file) {counter_struct.sdc}
set rda_Input(ui_io_file)        {}
#
# Leave min and max empty if you have only one timing library
# (space-separated if you have more than one)
set rda_Input(ui_timelib)        {example.lib}
set rda_Input(ui_timelib,min)    {}
set rda_Input(ui_timelib,max)    {}
#
# Set the name of your lef file(s) (space-separated if more than one). 
set rda_Input(ui_leffile) {example.lef}
#
# Include the footprints of your cells that fit these uses. Delay 
# can be an inverter or a buffer. Leave buf blank if you don't 
# have a non-inverting buffer. These are the "footprints" in 
# the .lib file, not the cell names. 
set rda_Input(ui_buf_footprint)      {}
set rda_Input(ui_delay_footprint)    {inv}
set rda_Input(ui_inv_footprint)      {inv}
set rda_Input(ui_cts_cell_footprint) {inv}
#
# You might want to set core utilization and core_to spacing
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_to_left) {30.0}
set rda_Input(ui_core_to_right) {30.0}
set rda_Input(ui_core_to_top) {30.0}
set rda_Input(ui_core_to_bottom) {30.0}
#
#########################################################
# Below here you should be able leave alone... 
#########################################################
#... For remaining lines, see Appendix ...