module counter (clk, clr, load, in, count); parameter width=8; input clk, clr, load; input [width-1 : 0] in; output [width-1 : 0] count; reg [width-1 : 0] tmp; always @(posedge clk or negedge clr) begin if (!clr) tmp = 0; else if (load) tmp = in; else tmp = tmp + 1; end assign count = tmp; endmodule