NCSU CDK Documentation - Technology Files

Note: $cdk_dir == toplevel directory of NCSU CDK

This document contains the following sections:

CDK Technology Files and Technology Libraries

NCSU provides a set of tech files for the SCMOS design rules provided by MOSIS. These were originally based on a set published by MIT but have been heavily expanded and updated for 4.4. The tech files define layer names, DRC and extraction rules and various other things.

For each process, the CDK includes a ``technology library'' against which design libraries can be linked. These technology libraries contain all the information held in the technology files and so eliminate the need for the design library to duplicate this information. The technology libraries are named ``NCSU_TechLib_xxxYY'', where ``xxx'' is an abbreviation of the foundry name, and ``YY'' is the minimum device length in microns, e.g., NCSU_TechLib_ami16 is for the AMI 1.6um process. Another string may optionally be appended to the library name if necessary, e.g. NCSU_TechLib_tsmc04_3M2P, where the _3M2P marks this as the three-metal, two-poly variant of the TSMC 0.4um (drawn) process.

The technology files which contain the ``controls'' class for each process are stored in the $cdk_dir/techfile directory. The files are named according to the template ``''. The current list of active process techfile stubs is: 

(Note that the TSMC 0.4um process has two distinct variants, because different mask layers are available depending on which variant is used.)

Note for 0.99.X users: The old technology library names, e.g., hp14_TechLib, have been kept for backward compatibility with existing designs. All files from the current technology library are linked to the old library. For example, in the directory hp14_TechLib are symbolic links to all files in the (current) directory NCSU_TechLib_hp06. This way, any design that references an instance from hp14_TechLib will still find it, even though the reference points (via the link) to NCSU_TechLib_hp06. In case you're wondering why we didn't simply make hp14_TechLib a link to NCSU_TechLib_hp06 itself, that would confuse the Library Manager, since there would be two libraries pointing to the same directory.

The control class defines the parameters ``lambda'' and ``technology'' for each process. Additionally, it defines the following parameters on a process-by-process basis:

    elecAvailable     - if elec (poly2) is available

npnAvailable - if pbase (for NPNs) is available

ccdAvailable - if ccd is available

metal3Available - if metal 3 is available

metal4Available - if metal 4 is available

metal5Available - if metal 5 is available

metal6Available - if metal 6 is available

metalcapAvailable - if metalcap is available

cwellAvailable - if linear thin-ox capacitors are available

polyCapAvailable - if second poly for capacitors is available

memsAvailable - if MEMS layers are available

sblockAvailable - if silicide block (for poly resistors) is available

highresAvailable - if high resistance poly2 implant is available

hvAvailable - if thick active (for high-voltage transistors) is available

See our list of layers and optional process features.

The technology files use these parameters to include rules for these optional layers only if they are available. This avoids the temptation for designers to attempt to place layers in their designs when that layer is not available for the given process.

The remaining tech files are loaded by the ``Create Library'' form.

Adding Support for a New Technology

Each process needs its own technology library against which users can link their design libraries. To create a new technology library for a new process:

  1. Create the master technology file (.tf file) with the appropriate techParams in the $cdk_dir/techfile directory. The name of the file needs to be the same as the ?techFile parameter in the NCSU_techData entry (see step 8) and should be constructed in accordance with the instructions above.

  2. If new layers were created that need new symbolics (such as metal layers that need symbolic contacts for path stitching), edit $cdk_dir/techfile/ to create the new symbolics. Then add their names to the list at the top of $cdk_dir/skill/menus/ciw/

  3. Add entries in $cdk_dir/cdssetup/display.drf for any new layers.

  4. Add the new technology library name to the list in $cdk_dir/skill/pcells/

  5. Add appropriate parasitic capacitances to the list in $cdk_dir/techfile/

  6. If the new technology has a combination of optional layers that is not already present in an existing technology:

  7. Update the table showing which processes have which optional layers in $cdk_dir/doc/layerInfo.html.

  8. In $cdk_dir/skill/, create an entry in the NCSU_techData table and fill in the appropriate values. Note that after this step, the technology choice will be visible in the ``Create Library'' dialog box, so make sure everything is done at this point.

  9. Using the ``File->Library->New...'' menu item, create the technology library in the directory $cdk_dir/lib (Be sure to choose the ``Compile Tech File'' option!)

Adding New Layers to the CDK

This list of ``things to do'' is geared toward new interconnect layers. If you add a new ``device'' layer, you may need to alter other files. (Note that you may have already done some of these things if you're adding a new process.)
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