/************************************************************* * Unfortunately, these don't compile properly if they're in the * physicalDesignAppRules.tf file. So, the procedure is to compile the * tech file in the UofU_Techlib_ami06 project, then merge this file * into the tech file of that new project. * Erik Brunvand, University of Utah *************************************************************/ ; ; I've never used the compactor, and I'm not sure I have these right, but ; just in case someone wants to try it, here are the rules... I believe this ; is for the Virtuoso-XL compactor, but again, I'm not sure. ; ;******************************** ; COMPACTOR RULES ;******************************** compactorRules( compactorLayers( ;( layer usage ) ;( ----- ----- ) ( metal1 "conduction" ) ( via "via" ) ( metal2 "conduction" ) ( via2 "via" ) ( metal3 "conduction" ) ( prBoundary "cellBoundary" ) ( ("metal1" "drawing") "conduction" ) ( ("via" "drawing") "via" ) ( ("metal2" "drawing") "conduction" ) ( ("via2" "drawing") "via" ) ( ("metal3" "drawing") "conduction" ) ) ;compactorLayers symWires( ;( name layer [(impLayer impSpacing)][(default min max)][(legalRegion regionLayer)][WLM] ) ( metal1 ("metal1" "drawing") nil (0.9 nil nil) nil 0.065 ) ( metal2 ("metal2" "drawing") nil (0.9 nil nil) nil 0.05 ) ( metal3 ("metal3" "drawing") nil (0.9 nil nil) nil 0.05 ) ) ;symWires ) ;compactorRules ; ;******************************** ; P&R RULES ;******************************** prRules( prRoutingLayers( ;( layer preferredDirection ) ;( ----- ------------------ ) ( metal1 "horizontal" ) ( metal2 "vertical" ) ( metal3 "horizontal" ) ) ;prRoutingLayers ; the M1_ce (contact to elec layer) is here just so abstract doesn't ; complain. ; prViaTypes( ;( device viewName viaType ) ;( --------------- ------- ) ; ( ("M1_P" "symbolic") "default" ) ; ( ("M1_N" "symbolic") "default" ) ; ( ("SUBTAP" "symbolic") "default" ) ; ( ("NTAP" "symbolic") "default" ) ( ("M1_POLY" "symbolic") "default" ) ( ("M2_M1" "symbolic") "default" ) ( ("M3_M2" "symbolic") "default" ) ( ("M1_ce" "symbolic") "default" ) ) ;prViaTypes ; ; These are the routing pitches defined in the .lef file for soc. Note ; that the metal1 pitch in particular is more than it has to be. It's ; defined this way to be in 1:1 ratio with the metal3 pitch which is the ; other horizontal routing layer... ; prRoutingPitch( ;( layer pitch ) ;( ----- ----- ) ( metal1 3.0 ) ( metal2 2.4 ) ( metal3 3.0 ) ) ;prRoutingPitch ; ; I'm going to edit the .lef file so that poly is the only masterslice ; layer defined. No sense confusing soc about layers that it can't ; use for routing... ; prMastersliceLayers( ;( layers : listed in order of lowest (closest to substrate) to highest ) ;( -------------------------------------------------------------------- ) ; ( nwell nactive pactive poly ) ( poly ) ) ;prMastersliceLayers ; ; These turns are defined in the .lef file... ; prViaRules( ;( ViaRuleName viaDeviceName(s) ; layer1 direction (wMin wMax overHang metalOverHang) ; layer2 direction (wMin wMax overHang metalOverHang) ; (properties) ;) ;( ---------------------------------------------------------------------- ) ( TURN1 nil metal1 "vertical" ( _NA_ _NA_ _NA_ _NA_ ) metal1 "horizontal" ( _NA_ _NA_ _NA_ _NA_ ) ) ( TURN2 nil metal2 "vertical" ( _NA_ _NA_ _NA_ _NA_ ) metal2 "horizontal" ( _NA_ _NA_ _NA_ _NA_ ) ) ( TURN3 nil metal3 "vertical" ( _NA_ _NA_ _NA_ _NA_ ) metal3 "horizontal" ( _NA_ _NA_ _NA_ _NA_ ) ) ) ;prViaRules ; ; These are also defined in the .lef file... ; prGenViaRules( ;( ViaRuleName viaLayer (lowerPt upperPt xPitch yPitch resistance) ; Layer1 Direction (wMin wMax overHang metalOverHang) ; Layer2 Direction (wMin wMax overHang metalOverHang) ; (properties) ;) ;( ---------------------------------------------------------------------- ) ( viagen21 "via" ( (range -0.3 -0.3) (range 0.3 0.3) 1.5 1.5 _NA_ ) metal1 "horizontal" ( 1.2 120.0 0.3 0.0 ) metal2 "vertical" ( 1.2 120.0 0.3 0.0 ) ) ( viagen32 "via2" ( (range -0.3 -0.3) (range 0.3 0.3) 2.1 2.1 _NA_ ) metal3 "horizontal" ( 1.8 180.0 0.6 0.0 ) metal2 "vertical" ( 1.2 120.0 0.3 0.0 ) ) ) ;prGenViaRules ) ;prRules