################################################
#  Encounter Input configuration file          #
#  Erik Brunvand                               #
#  University of Utah                          #
################################################
global rda_Input
#
#########################################################
# Here are the parts you need to update for your design
#########################################################
#
# Your input is structural verilog. Set the top module name 
# and also give the .sdc file you used in synthesis for the 
# clock timing constraints. 
set rda_Input(ui_netlist)        {<filename>.v}
set rda_Input(ui_topcell)        {<TopCellName>}
set rda_Input(ui_timingcon_file) {<filename>.sdc}
set rda_Input(ui_io_file)        {<filename>.io]
#
# Leave min and max empty if you have only one timing library
# (space-separated if you have more than one)
set rda_Input(ui_timelib)        {<filename>.lib}
set rda_Input(ui_timelib,min)    {}
set rda_Input(ui_timelib,max)    {}
#
# Set the name of your lef file or files 
# (space-separated if you have more than one). 
set rda_Input(ui_leffile) {<filename>.lef}
#
# Include the footprints of your cells that fit these uses. Delay 
# can be an inverter or a buffer. Leave buf blank if you don't 
# have a non-inverting buffer. These are the "footprints" in 
# the .lib file, not the cell names. 
set rda_Input(ui_buf_footprint)      {<buf>}
set rda_Input(ui_delay_footprint)    {<delay>}
set rda_Input(ui_inv_footprint)      {<inv>}
set rda_Input(ui_cts_cell_footprint) {<cts-cell>}
#
#########################################################
# You might want to set core utilization and core_to spacing
# or you can leave these defaults... 
#########################################################
#
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_to_left) {30.0}
set rda_Input(ui_core_to_right) {30.0}
set rda_Input(ui_core_to_top) {30.0}
set rda_Input(ui_core_to_bottom) {30.0}
#
#########################################################
# Below here you should be able to leave alone... 
#########################################################
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 }
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_settop) {1}
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R180}
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {120.0ps}
set rda_Input(ui_defcap_scale) {1.0}
set rda_Input(ui_detcap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {0}
set rda_Input(ui_pwrnet) {vdd!}
set rda_Input(ui_gndnet) {gnd!}
set rda_Input(ui_pg_connections) [list \
                        {PIN:*.vdd!:} \
                        {PIN:*.gnd!:} \
                        {TIEHI::} \
                        {TIELO::} \
                              ]
set rda_Input(PIN:*.vdd!:) {vdd!}
set rda_Input(PIN:*.gnd!:) {gnd!}
set rda_Input(TIEHI::) {vdd!}
set rda_Input(TIELO::) {gnd!}